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83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference preliminary specification supersedes data of 1997 dec 03 ic20 data handbook 1998 apr 23 integrated circuits
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 2 1998 apr 23 description the philips 83c754/87c754 offers many of the advantages of the 80c51 architecture in a small package and at low cost. the 8xc754 microcontroller is fabricated with philips high-density cmos technology. philips epitaxial substrate minimizes cmos latch-up senitivity. the 8xc754 contains a 4k 8 rom (83c754) eprom (87c754), a single module pca, a 256 8 ram, 11 i/o lines, two 16-bit counter/timers, a two-priority level interrupt structure, a full duplex serial channel, an on-chip oscillator, and an 8-bit d/a converter. the eprom version of this device, the 87c754, is available in plastic one-time programmable (otp) packages. once the array has been programmed, it ifs functionally equivalent to the masked rom 83c754. thus, unless explicitly stated otherwise, all references made to the 87c754 apply equally to the 83c754. the 8xc754 supports two power reduction modes of operation referred to as the idle mode and the power-down mode. features ? available in erasable quartz lid or one-time programmable plastic packages ? 80c51-based architecture ? small package sizes 28-pin ssop ? wide oscillator frequency range ? power control modes: idle mode power-down mode ? 4k 8 rom (83c754) eprom (87c754) ? 256 8 ram ? two 16-bit auto reloadable counter/timers ? single module pca counter/timer ? full duplex serial channel ? boolean processor ? cmos and ttl compatible pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 28 rxd/t0/p3.4/d4 txd/t1/p3.5/d5 eci/p3.6/d6 int1/p3.7/d7 rst x2 x1 v ss zin/a2/a10 yin/a3/a11 xin/a4 p3.3/d3 p3.2/d2 p3.1/d1 p3.0/d0 int0/p1.0/a0/a8 cex/p1.1/a1/a9 v cc xydac/a7 v pp /p1.2 zdac/asel xysource/a6 xydacbias/pgm xyzramp/a5 13 16 vreg av ss 14 15 decouple av cc su00665d ceramic dual in-line package and plastic shrink small outline package part number selection rom eprom 1 temperature range c and package frequency drawing number p83c754ebd db p87c754ebd db otp 0 to +70, 28-pin shrink small outline package 3.5 to 16mhz sot341-1 note: 1. otp = one time programmable eprom. uv = uv erasable eprom.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 3 block diagram rst x1 x2 v cc v ss ram rom/ eprom acc tmp2 tmp1 alu instruction register pd oscillator psw buffer dptr pcon tcon ie th0 tl0 th1 tl1 interrupt, serial port and timer blocks p1.0p1.2 p3.0p3.7 dac av ss av cc ram addr register stack pointer program address register pc incre- menter program counter port 3 drivers port 1 drivers port 3 latch port 1 latch timing and control b register su00666d analog x in xyzramp decouple vreg xydacbias xysource zdac xydac
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 4 pin description mnemonic dip pin no. type name and function v ss 8 i circuit ground potential. v cc 22 i supply voltage during normal, idle, and power-down operation. p1.0p1.2 21, 23, 24 i/o port 1: port 1 is a 3-bit bidirectional i/o port with internal pull-ups on p1.0 and p1.1. port 1 pins that have 1s written to them can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups (p1.0, p1.1). (see dc electrical characteristics: i il ). port 1 also serves the special function features listed below (note: p1.0 does not have the strong pullup that is on for 2 oscillator periods.): 24 i int0 (p1.0): external interrupt 0. 23 o cex (p1.1): pca clock output. 21 i v pp (p1.2): programming voltage input (open drain). p3.0p3.7 14, 2528 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also functions as the data input for the eprom memory location to be programmed (or verified). (note: p3.5 does not have the strong pullup that is on for 2 oscillator periods.) port 3 also serves the special function as listed below: 3 i eci (p3.6): external pca clock input. 1 i rxd/t0 (p3.4): serial port receiver data input. timer 0 external clock input. 4 i int1 : external interrupt 1. 2 i txd/t1 (p3.5): serial port transmitter data. timer 1 external clock input. rst 5 i reset: a high on this pin for two machine cycles while the oscillator is running resets the device. after the device is reset, a 10-bit serial sequence, sent lsb first, applied to reset, places the device in the programming state allowing programming address, data and v pp to be applied for programming or verification purposes. the reset serial sequence must be synchronized with the x1 input. (note: the 83/87c754 does not have an internal reset resistor.) x1 7 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. x1 also serves as the clock to strobe in a serial bit stream into reset to place the device in the programming state. x2 6 o crystal 2: output from the inverting oscillator amplifier. av cc 1 14 i analog supply voltage and reference input. av ss 1 13 i analog supply and reference ground. zin 9 i zin: input to analog multiplexer. yin 10 i yin: input to analog multiplexer. xin 11 i xin: input to analog multiplexer. xyzramp 12 o xyzramp: provides a low impedance pulldown to v ss under s/w control. decouple 15 o decouple: output from regulated supply for connection of decoupling capacitors. vreg 16 o vreg: provides regulated analog supply output. xydacbias 17 o xydacbias: provides source voltage for bias of external circuitry. input which specifies verify mode (output enable) or the program mode. /pgm = 1 output enabled (verify mode). /pgm = 0 program mode. xysource 18 o xysource: provides source voltage from regulated analog supply. zdac 19 o zdac: switchable outp from the internal dac. asel (p0.0) input which indicates which bits of the eprom address are applied to port 3. asel = 0 low address byte available on port 3. asel = 1 high address byte available on port 3 (only the three least significant bits are used). xydac 20 o xydac: non-switchable output from the internal dac. note: 1. av ss (reference ground) must be connected to 0v (ground). av cc (reference input) cannot differ from v cc by more than 0.2v, and must be in the range 4.5v to 5.5v.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 5 oscillator characteristics x1 and x2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. to drive the device from an external clock source, x1 should be driven while x2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. idle mode the 8xc754 includes the 80c51 power-down and idle mode features. in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. upon powering-up the circuit, or exiting from idle mode, sufficient time must be allowed for stabilization of the internal analog reference voltages before a d/a conversion is started. special function registers the special function registers (directly addressable only) contain all of the 8xc754 registers except the program counter and the four register banks. most of the special function registers are used to control the on-chip peripheral hardware. other registers include arithmetic registers (acc, b, psw), stack pointer (sp) and data pointer registers (dph, dpl). twelve of the sfrs are bit addressable. data pointer the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). in the 80c51 this register allows the access of external data memory using the movx instruction. since the 83c754 does not support movx or external memory accesses, this register is generally used as a 16-bit offset pointer of the accumulator in a movc instruction. dptr may also be manipulated as two independent 8-bit registers. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. a hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register pcon. table 1. external pin status during idle and power-down modes mode port 1 port 3 idle data data power-down data data standard serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. mode 3: 11 its are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 2 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 9 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that were not being addressed leave their sm2s set, and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 6 serial port control register the serial port control and status register is the special function register scon, shown in figure 1. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12. the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. mode 2 baud rate 2 smod 64 (oscillator frequency) in the 8xc754, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate 2 smod 32 (timer 1 overflow rate) the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate 2 smod 32 oscillator frequency 12 [256 (th1)] one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 2 lists various commonly used baud rates and how they can be obtained from timer 1. sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was no t received. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the o ther modes, in any serial transmission. must be cleared by software. ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the o ther modes, in any serial reception (except see sm2). must be cleared by software. msb lsb sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc / 12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 1 1 3 9-bit uart variable su00120 figure 1. ba d rate f osc smod timer 1 ba u d rate f osc smod c/t mode reload value mode 0 max: 1.67mhz 20mhz x x x x mode 2 max: 625k 20mhz 1 x x x mode 1, 3 max: 104.2k 20mhz 1 0 2 ffh 19.2k 11.059mhz 1 0 2 fdh 9.6k 11.059mhz 0 0 2 fdh 4.8k 11.059mhz 0 0 2 fah 2.4k 11.059mhz 0 0 2 f4h 1.2k 11.059mhz 0 0 2 e8h 137.5 11.986mhz 0 0 2 1dh 110 6mhz 0 0 2 72h 110 12mhz 0 0 1 feebh figure 2. timer 1 generated commonly used baud rates
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 7 differences between the 8xc754 and the 80c51 program memory on the 8xc754, program memory is 4096 bytes long and is not externally expandable, so the 80c51 instructions movx, ljmp, and lcall are not implemented. if these instructions are executed, the appropriate number of instruction cycles will take place along with external fetches; however, no operation will take place. the ljmp may not respond to all program address bits. the only fixed locations in program memory are the addresses at which execution is taken up in response to reset and interrupts, which are as follows: program memory event address reset 000 external int0 003 timer 0 00b external int1 013 pca 01b sio/tf1 023 memory organization the 8xc754 manipulates operands in three memory address spaces. the first is the program memory space which contains program instructions as well as constants such as look-up tables. the program memory space contains 4k bytes in the 8xc754. the second memory space is the data memory array which has a logical address space of 256 bytes. the third memory space is the special function register array having a 128-byte address space (80h to ffh). only selected locations in this memory space are used (see table 2). note that the architecture of these memory spaces (internal program memory, internal data memory, and special function registers) is identical to the 80c51, and the 8xc754 varies only in the amount of memory physically implemented. the 8xc754 does not directly address any external data or program memory spaces. for this reason, the movx instructions in the 80c51 instruction set are not implemented in the 83c754, nor are the alternate i/o pin functions rd and wr . i/o ports the i/o pins provided by the 8xc754 consist of port 1 and port 3. port 1 port 1 is a 3-bit bidirectional i/o port and includes alternate functions on some pins of this port. p1.1 is provided with internal pullups while the remaining pins (p1.0 and p1.2) are an open drain output structure. the alternate functions for port 1 are: int0 external interrupt 0. pcaout pca clock output v pp external programming voltage. port 3 port 3 is an 8-bit bidirectional i/o port structure. p3.5 is open drain. the alternate functions for port 3 are: rxd serial port receiver data input. t1 timer 1 external clock input. int1 external interrupt 1. txd serial port transmitter data. t0 timer 0 external clock input. eci pca external clock input. analog section the analog section of the 8xc754, shown in figure 3, consists of four major elements: a bandgap referenced voltage regulator, an 8-bit dac, an input multiplexer and comparator, and a low impedance pulldown device. the bandgap voltage regulator uses the av cc pin as its supply and produces a regulated output on the vreg pin. the bandgap reference is enabled/disabled by ac0. the regulator also supplies the analog supply voltage for the dac. the regulator may be switched on/off by means of the ac1 bit in the analog control register (acon0). the regulator output may also be supplied to the xydacbias and xysource pins by means of bits ac3 and ac4, respectively. the decouple pin is provided for decoupling the regulator output. the dac is an 8-bit device and its output appears on the xydac pin. in addition, the dac output may also be routed to the zdac pin by means of bit ac6 in the acon0 register. the dac output is not buffered, so external load impedances should be taken into consideration when using either of these outputs. a 3-input multiplexer is provided, whose output is connected to the positive reference of a comparator. the multiplexer output is controlled by bits mux2:0 of acon1. a bandgap reference supplies the negative reference of the comparator. the output of the comparator may be used the trigger the capture input of pca module. a low impedance pulldown is supplied at the xyzramp pin and is controlled by bit ac5 of acon0. interrupt subsystemefixed priority the interrupt structure is a seven-source, two-level interrupt system. simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows: highest priority: pin int0 timer flag 0 pin int1 lowest priority: pin int1 pca serial i/o tf1 the vector addresses are as follows: source vector address int0 0003h tf0 000bh int1 0013h pca 001bh sio/tf1 0023h interrupt enable register msb lsb ea es/t1 ec ex1 et0 ex0 position symbol function ie.7 ea global interrupt disable when ea = 0 ie.6 ie.5 ie.4 es/t1 serial port/timer flag 1 ie.3 ec pca interrupt ie.2 ex1 external interrupt 1 ie.1 et0 timer 0 overflow ie.0 ex0 external interrupt 0
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 8 av cc decouple vreg bandgap ref* ac2 xydacbias 20k 10k xysource xydac ac4 ac3 zdac 1k ac6 analog mux zin yin xin mux0 mux1 to pca trigger bandgap ref xyzramp ac5 su00765a ac1 *enabled/disabled by ac0 ext ac7 mux2 dcon 7:0 (84h) figure 3. analog section latch dq cl q read latch int. bus write to latch read pin alternate input function v dd pin internal* pull-up alternate output function su00671 *pins listed as open drain will not have this pullup figure 4. typical port bit latches and i/o buffers
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 9 table 2. 8xc754 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h acon0* analog control 0 a0h ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 acon1* analog control 1 c0h tsi mux2 mux1 mux0 b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ccaph# pca module capture high feh ccapl# pca module capture low eeh ccapm# pca module mode deh ecom capp capn mat tog pwm eccf x0000000b df de dd dc db da d9 d8 ccon*# pca counter control d8h cf cr ccf4 00x00000b ch# pca counter high f9h 00h cl# pca counter low e9h 00h cmod# pca counter mode d9h codl wdte cps1 cps0 ecf 00xxx000b dcon dac control 84h dptr: dpl dph data pointer (2 bytes) data pointer low data pointer high 82h 83h 00h 00h af ae ad ac ab aa a9 a8 ie*# interrupt enable a8h ea es/t1 ec ex1 et0 ex0 00h af ae ad ac ab aa a9 a8 ip* interrupt priority b8h ps/t1 ppc px1 pt0 px0 x0000000b 84 83 82 81 80 xxx1 1111b p1*# port 1 90h zin xyzramp xysource p3*# port 3 b0h int1 eci txd rxd pcon power control 87h smod1 smod0 pof gf1 gf0 pd idl 00xxxx00b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h sbuf serial data buffer 99h xxxxxxxxb sp stack pointer 81h 07h 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h c7 c6 c5 c4 c3 c2 c1 c0 * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 10 counter/timer the 8xc754 counter/timers are designated timer 0 and 1. they are identical to the 80c51 counter/timers. (timer 1 shares its interrupt with the serial port.) programmable counter array (pca) the programmable counter array is a special timer that has one 16-bit capture/compare module associated with it. the module can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. the basic pca configuration is shown in figure 5. the pca timer can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the timer 0 overflow, or the input on the eci pin (p3.1). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 8): cps1 cps0 pca timer count source 0 0 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 0 timer 0 overflow 1 1 external input at eci pin in the cmod sfr are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function, and ecf which when set causes an interrupt and the pca overflow flag, cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 6. the watchdog timer function is implemented in module 4 as implemented in other parts that have a pca that are available on the market. the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and module (refer to figure 9). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bit 4 of the ccon register is the flag for the module and is set by hardware when either a match or a capture occurs. this flag can only be cleared by software. the pca interrupt system shown in figure 7. the ccapm register contains the bits that control the mode in which the module will operate. the eccf bit enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapm.1) enables the pulse width modulation mode. the tog bit (ccapm.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapm.3), when set, will cause the ccf bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapm.4) and capp (ccapm.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapm.6) when set enables the comparator function. figure 11 shows the ccapm settings for the various pca functions. there are two additional registers associated with the pca module. they are ccaph and ccapl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when the module is used in the pwm mode these registers are used to control the duty cycle of the output. pca capture mode to use the pca module in the capture mode, either one or both of the ccapm bits capn and capp must be set. the external cex input for the module is sampled for transition. when a valid transition occurs, the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapl and ccaph). if the ccf bit for the module in the ccon sfr and the eccf bit in the ccapm sfr are set, then an interrupt will be generated. refer to figure 12. 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the module's ccapm register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccf (ccon sfr) and the eccf (ccapm sfr) bits for the module are both set (see figure 13). high speed output mode in this mode the cex output associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapm sfr must be set (see figure 14). pulse width modulator mode the pca module can be used as a pwm output. figure 15 shows the pwm function. the frequency of the output depends on the source for the pca timer. the duty cycle of the module is independently variable using the module's capture register ccapl. when the value of the pca cl sfr is less than the value in the module's ccapl sfr, the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapl is reloaded with the value in ccaph. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapm register must be set to enable the pwm mode. module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer pca module p1.1/cex 16 bits pca timer/counter time base for pca modules 16 bits su00672b figure 5. programmable counter array (pca)
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 11 cf cr ccf ccon (d8h) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (d9h) cidl wdte cps1 cps0 ecf osc/12 osc/4 timer 0 overflow external input (p3.6/eci) decode 00 01 10 11 su00673b figure 6. pca timer/counter pca module pca timer/counter cf cr ccf cmod.0 ecf ccapm to interrupt priority decoder ccon (d8h) ie.6 ec ie.7 ea su00674a eccfn figure 7. pca interrupt system
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 12 cmod address = od9h reset value = 00xx x000b cidl wdte cps1 cps0 ecf bit addressable bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input** 0 0 0 internal clock, f osc 12 0 1 1 internal clock, f osc 4 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p3.1 pin (max. rate = f osc 8) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su00675a 76543210 figure 8. cmod: pca counter mode register ccon address = od8h reset value = 00x0 0000b cf cr ccf bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf pca module interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su00676a 76543210 figure 9. ccon: pca counter control register
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 13 ccapmn address ccapm 0deh reset value = x000 0000b ecom capp capn mat tog pwm eccf not bit addressable bit: symbol function not implemented, reserved for future use*. ecom enable comparator. ecom = 1 enables the comparator function. capp capture positive, capp = 1 enables positive edge capture. capn capture negative, capn = 1 enables negative edge capture. mat match. when mat = 1, a match of the pca counter with this module's compare/capture register causes the ccf bit in ccon to be set, flagging an interrupt. tog toggle. when tog = 1, a match of the pca counter with this module's compare/capture register causes the cex pin to toggle. pwm pulse width modulation mode. pwm4 = 1 enables the cex pin to be used as a pulse width modulated output. eccf enable ccf interrupt. enables compare/capture flag ccf in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su00677a 76543210 figure 10. ccapm: pca modules compare/capture registers ecom capp capn mat tog pwm eccf module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cex x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cex x x 1 1 0 0 0 x 16-bit capture by a transition on cex x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 11. pca module modes (ccapm register) cf cr ccf ccon (d8h) ecom capp capn mat tog pwm eccf ccapm ch cl ccaph ccapl cex capture pca interrupt pca timer/counter 0 000 (to ccf) su00678a figure 12. pca capture mode
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 14 match cf cr ccf ccon (d8h) ecom capp capn mat tog pwm eccf ccapm ch cl ccaph ccapl pca interrupt pca timer/counter 00 00 16bit comparator (to ccf) enable write to ccaph reset write to ccapl 01 su00679a figure 13. pca compare mode cf cr ccf ccon (d8h) ecom capp capn mat tog pwm eccf ccapm ch cl ccaph ccapl pca interrupt pca timer/counter 10 00 16bit comparator (to ccf4) write to ccaph reset write to ccapl 01 enable cex toggle match su00680a figure 14. pca high speed output mode
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 15 cl < ccapl ecom capp capn mat tog pwm eccf ccapm pca timer/counter 00 00 cl ccapl cex 8bit comparator overflow ccaph enable 0 1 cl >= ccapl 0 su00681a figure 15. pca pwm mode ecom capp capn mat tog pwm eccf ccapm (deh) ch cl ccaph ccapl reset pca timer/counter x0 00 16bit comparator match enable write to ccaph reset write to ccapl 01 1 cmod (d9h) cidl wdte cps1 cps0 ecf x su00682a figure 16. pca watchdog timer
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 16 absolute maximum ratings 1, 3, 4 parameter rating unit storage temperature range 65 to +150 c voltage from v cc to v ss 0.5 to +6.5 v voltage from any pin to v ss (except v pp ) 0.5 to v cc + 0.5 v power dissipation 1.0 w voltage from v pp pin to v ss 0.5 to + 13.0 v dc electrical characteristics t amb = 0 c to +70 c, av cc = 5v 5, av ss = 0v 4 v cc = 5v 10%, v ss = 0v symbol parameter test conditions limits 4 unit symbol parameter test conditions min typ 1 max unit i cc supply current (see figure 19) inputs v il input low voltage, port 1, 3 0.5 0.2v cc 0.1 v v ih input high voltage, port 1, 3 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, x1, rst 0.7v cc v cc +0.5 v outputs v ol output low voltage, port 3 i ol = 1.6ma 2 0.45 v v ol1 output low voltage, port 1.0, 1.1, 1.2 i ol = 3.2ma 2 0.45 v v oh output high voltage, ports 3, 1.0, 1.1 i oh = 60 m a, 2.4 v i li input leakage current, port 1, 3, rst 0.45 < v in < v cc +10 m a i il logical 0 input cirrent, ports 1 and 3 v in = 0.45v 50 m a c io pin capacitance test freq = 1mhz, t amb = 25 c 10 pf i pd power-down current 5 v cc = 2 to 5.5v v cc = 2 to 6.0v (83c754) 50 m a v pp v pp program voltage (87c754 only) v ss = 0v v cc = 5v 10% t amb = 21 c to 27 c 12.5 13.0 v i pp program current (87c754 only) v pp = 13.0v 50 ma notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. under steady state (non-transient) conditions, iol must be externally limited as follows: maximum i ol per port pin: 10ma maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 67ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 4. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 5. power-down i cc is measured with all output pins disconnected; port 0 = v cc ; x2, x1 n.c.; rst = v ss . 6. i cc is measured with all output pins disconnected; x1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc 0.5v; x2 n.c.; rst = port 0 = v cc . i cc will be slightly higher if a crystal oscillator is used. 7. idle i cc is measured with all output pins disconnected; x1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc 0.5v; x2 n.c.; port 0 = v cc ; rst = v ss . 8. load capacitance for ports = 80pf.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 17 analog section electrical characteristics t amb = 0 c to +70 c, av cc = 5v 5, av ss = 0v 4 v cc = 5v 10%, v ss = 0v symbol parameter test conditions limits 4 unit symbol parameter test conditions min typ 1 max unit analog inputs (d/a guaranteed only with quartz window covered.) av cc analog supply voltage 4.5 5.5 v sensor resistor 330 3k w iav cc ac0 = 0 ic only 0.88 1.5 ma ac0 = 1 10 m a regulator vreg 3.6 3.8 4.0 v ivreg 13 55 ma cdecouple stability requirement 3 10 m f rdsonq1 7 w ileakageq1 tbd m a ileakageq2 tbd m a psrr 100hz 40 db vregrej vreg rejection of 1 volt av cc step change 100 100 mv tvreg vreg turn on time q1 off, 330 w sensor 2 5 ms mux and comparator comparator trip point 1.14 1.26 1.38 v comparator delay input 0.04v/ m s 50 ns comparator delay change av cc 4.5 to 5.5v 10 2 10 ns mux impedance 1 k w ileakagemux tbd m a digital-to-analog conversion zdac, xydac monotonicity 0 bits zdac, xydac impedance 10 k w dac selection switch impedance 40 w dac settling 1 m s zdac switch impedance 50 w zdac switch impedance change av cc 4.5 to 5.5v 20 20 w zdac switch leakage tbd m a switches xyzramp impedance 25 100 w xyzramp impedance change av cc 4.5 to 5.5v 25 25 w xyzramp leakage tbd m a xyzramp discharge to 1lsb (1.6mv) 1.5 10 m s xyzramp delay turn on time 6 50 ns xyzramp start time change av cc 4.5 to 5.5v 10 10 ns xydacbias impedance 7 13 w xydacbias leakage tbd m a xydacbias switching time 130 1000 ns xysource impedance 150 300 w xysource impedance change av cc 4.5 to 5.5v 100 100 w xysource leakage tbd m a xysource switching time 30 500 ns
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 18 ac electrical characteristics t amb = 0 c to +70 c, v cc = 5v 10%, v ss = 0v 4, 8 16mhz clock variable clock symbol parameter min max min max unit 1/t clcl oscillator frequency 3.5 16 mhz external clock (figure 17) t chcx high time 20 20 ns t clcx low time 20 20 ns t clch rise time 20 20 ns t chcl fall time 20 20 ns explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: c clock d input data h logic level high l logic level low q output data t time v valid x no longer a valid logic level z float t chcl t clcl t clch t chcx v cc 0.5 0.45v 0.2 v cc + 0.9 0.2 v cc 0.1 t clcx su00297 figure 17. external clock drive 0.2 v cc + 0.9 0.2 v cc 0.1 v cc 0.5 0.45v su00307 figure 18. ac testing input/output
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 19 4mhz 8mhz 12mhz 16mhz freq max active i cc 6 typ active i cc 6 max idle i cc 7 typ idle i cc 7 i cc ma 2 4 6 8 10 12 14 16 18 20 22 su00308 figure 19. i cc vs. freq maximum i cc values taken at v cc = 5.5v and worst case temperature. typical i cc values taken at v cc = 5.0v and 25 c. notes 6 and 7 refer to ac electrical characteristics. rom code submission when submitting rom code for the 83c754, the following must be specified: 1. 4k byte user rom data 2. 64 byte rom encryption key 3. rom security bits. address content bit(s) comment 0000h to 0fffh data 7:0 user rom data 1000h to 101fh key 7:0 rom encryption key ffh = no encryption 1020h sec 0 rom security bit 1 0 = enable security 1 = disable security 1020h sec 1 rom security bit 2 0 = enable security 1 = disable security security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea# is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box, and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 20 programming considerations eprom characteristics the 87c754 is programmed by using a modified quick-pulse programming algorithm similar to that used for devices such as the 87c751 and 87c752. figure 20 shows a block diagram of the programming configuration for the 87c754. port pin p0.2 is used as the programming voltage supply input (v pp signal). port pin p0.1 is used as the program (pgm/) signal. this pin is used for the 5 programming pulses. port 3 is used as the address input for the byte to be programmed and accepts both the high and low components of the eleven bit address. multiplexing of these address components is performed using the asel input. the user should drive the asel input high and then drive port 3 with the high order bits of the address. asel should remain high for at least 13 clock cycles. asel may then be driven low which latches the high order bits of the address internally. the high address should remain on port 3 for at least two clock cycles after asel is driven low. port 3 may then be driven with the low byte of the address. the low address will be internally stable 13 clock cycles later. the address will remain stable provided that the low byte placed on port 3 is held stable and asel is kept low. note: asel needs to be pulsed high only to change the high byte of the address. port 1 is used as a bidirectional data bus during programming and verify operations. during programming mode, it accepts the byte to be programmed. during verify mode, it provides the contents of the eprom location specified by the address which has been supplied to port 3. the xtal1 pin is the oscillator input and receives the master system clock. this clock should be between 1.2 and 16mhz. the reset pin is used to accept the serial data stream that places the 87c754 into various programming modes. this pattern consists of a 10-bit code with the lsb sent first. each bit is synchronized to the clock input, x1. programming operation figures 21 and 22 show the timing diagrams for the program/verify cycle. reset should initially be held high for at least two machine cycles. p0.1 (pgm/) and p0.2 (v pp ) will be at v oh as a result of the reset operation. at this point, these pins function as normal quasi-bidirectional i/o ports and the programming equipment may pull these lines low. however, prior to sending the 10-bit code on the reset pin, the programming equipment should drive these pins high (v ih ). the reset pin may now be used as the serial data input for the data stream which places the 87c754 in the programming mode. data bits are sampled during the clock high time and thus should only change during the time that the clock is low. following transmission of the last data bit, the reset pin should be held low. next the address information for the location to be programmed is placed on port 3 and asel is used to perform the address multiplexing, as previously described. at this time, port 1 functions as an output. a high voltage v pp level is then applied to the v pp input (p0.2). (this sets port 1 as an input port). the data to be programmed into the eprom array is then placed on port 1. this is followed by a series of programming pulses applied to the pgm/ pin (p0.1). these pulses are created by driving p0.1 low and then high. this pulse is repeated until a total of 5 programming pulses have occurred. at the conclusion of the last pulse, the pgm/ signal should remain high. the v pp signal may now be driven to the v oh level, placing the 87c754 in the verify mode. (port 1 is now used as an output port). after four machine cycles (48 clock periods), the contents of the addressed location in the eprom array will appear on port 1. the next programming cycle may now be initiated by placing the address information at the inputs of the multiplexed buffers, driving the v pp pin to the v pp voltage level, providing the byte to be programmed to port1 and issuing the 5 programming pulses on the pgm/ pin, bringing v pp back down to the v c level and verifying the byte. programming modes the 87c754 has four programming features incorporated within its eprom array. these include the user eprom for storage of the application's code, a 64-byte encryption key array and two security bits. programming and verification of these four elements are selected by a combination of the serial data stream applied to the reset pin and the voltage levels applied to port pins p0.1 and p0.2. the various combinations are shown in table 3. encryption key table the 87c754 includes a 64-byte eprom array that is programmable by the end user. the contents of this array can then be used to encrypt the program memory contents during a program memory verify operation. when a program memory verify operation is performed, the contents of the program memory location is xnor'ed with one of the bytes in the 64-byte encryption table. the resulting data pattern is then provided to port 1 as the verify data. the encryption mechanism can be disabled, in essence, by leaving the bytes in the encryption table in their erased state (ffh) since the xnor product of a bit with a logical one will result in the original bit. the encryption bytes are mapped with the code memory in 64-byte groups. the first byte in code memory will be encrypted with the first byte in the encryption table; the second byte in code memory will be encrypted with the second byte in the encryption table and so forth up to and including the 64th byte. the encryption repeats in 64-byte groups; the 65th byte in the code memory will be encrypted with the first byte in the encryption table, and so forth. security bits two security bits, security bit 1 and security bit 2, are provided to limit access to the user eprom and encryption key arrays. security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. additional programming of the user eprom is inhibited. 2. additional programming of the encryption key is inhibited. 3. verification of the encryption key is inhibited. 4. verification of the user eprom and the security bit levels may still be performed. (if the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. such programming would provide data during a verify cycle that is the logical complement of the user eprom contents). security bit 2, the verify inhibit bit, prevents verification of both the user eprom array and the encryption key arrays. the security bit levels may still be verified.
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 21 programming and verifying security bits security bits are programmed employing the same techniques used to program the user eprom and key arrays using serial data streams and logic levels on port pins indicated in table 3. when programming either security bit, it is not necessary to provide address or data information to the 87c754 on ports 1 and 3. verification occurs in a similar manner using the reset serial stream shown in table 3. port 3 is not required to be driven and the results of the verify operation will appear on ports 1.6 and 1.7. ports 1.7 contains the security bit 1 data and is a logical one if programmed and a logical zero if erased. likewise, p1.6 contains the security bit 2 data and is a logical one if programmed and a logical zero if erased. erasure characteristics erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. for this and secondary effects, it is recommended that an opaque label be placed over the window. for elevated temperature or environments where solvents are being used, apply kapton tape flourless part number 23455 or equivalent. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000uw/cm 2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1s state. table 3. implementing program/verify modes operation serial code pgm v pp program user eprom 296h * v pp verify user eprom 296h v ih v ih program key eprom 292h * v pp verify key eprom 292h v ih v ih program security bit 1 29ah * v pp program security bit 2 298h * v pp verify security bits 29ah v ih v ih note: * pulsed from v ih to v il and returned to v ih .
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 22 eprom programming and verification t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v symbol parameter min max unit 1/t clcl oscillator/clock frequency 1.2 16 mhz t avgl 1 address setup to pgm low 10 m s + 24t clcl t ghax address hold after pgm high 48t clcl t dvgl data setup to pgm low 38t clcl t dvgl data setup to pgm low 38t clcl t ghdx data hold after pgm high 36t clcl t shgl v pp setup to pgm low 10 m s t ghsl v pp hold after pgm 10 m s t glgh pgm width 90 110 m s t avqv 2 v pp low (v cc ) to data valid 48t clcl t ghgl pgm high to pgm low 10 m s t synl p0.0 (sync pulse) low 4t clcl t synh p0.0 (sync pulse) high 8t clcl t masel asel high time 13t clcl t mahld address hold time 2t clcl t haset address setup to asel 13t clcl t adsta low address to address stable 13t clcl notes: 1. address should be valid at least 24t clcl before the rising edge of v pp . 2. for a pure verify mode, i.e., no program mode in between, t avqv is 14t clcl maximum. a0a10 address strobe programming pulses v pp /v ih voltage source clk source reset control logic 87c754 zdac/asel xydacbias/pgm p1.2/v pp x1 rst v cc v ss p3.0p3.7 +5v data bus su00667a a0a10 figure 20. programming configuration
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 23 min 2 machine cycles ten bit serial code bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 undefined undefined xtal1 reset v pp pgm su00721 figure 21. entry into program/verify modes 5v 12.75v 5v 5 pulses t shgl t ghsl t glgh t ghgl 98 m s min 10 m s min t masel t haset t hahld t adsta t dvgl t ghdx t avqv verify mode program mode verify mode v pp pgm asel a0a10 d0d7 invalid data valid data data to be programmed invalid data valid data high address low address su00683a figure 22. program/verify cycle
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 24 ssop28: plastic shrink small outline package; 28 leads; body width 5.3mm sot341-1
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 25 notes
philips semiconductors preliminary specification 83c754/87c754 80c51 8-bit microcontroller family 4k/256 otp/rom, dac, comparator, uart, reference 1998 apr 23 26 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 05-98 document order number: 9397 750 03892
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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